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'[EE] How would you ensure fast power ramp up rise '
2012\05\22@024405 by Electron

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Hi,
I have a IC which, in the datasheet, is said to need a powerup rise time not
slower than 100uS in order to initialize correctly. Effectively it doesn't work
if the power ramps up slow, and there's no reset input, power must be disconnected
in order to attempt a new successfull turn on.

How would you ensure fast powerup rise time? The power turns on / ramps up very
slowly, and I can't help it.

I am currently investigating two options:

1) a PNP/NPN or PMOS/NPN pass circuit at the output, and using a voltage regulator
with error output (LP2951): when the error is signaled, no power is passed to the IC.
I would prefer to power the problematic IC directly via the error output, but it sinks
too much current (even 50 mA), so the PNP/NPN power switch is necessary, but it will
introduce a voltage drop, which is gonna cause errors (it's an analogue IC)..

2) using a voltage supervisor (e.g. NCP302HSN40T1G) BEFORE the voltage regulator, to
control the shutdown pin of the latter (a LP2951). Seems like a good idea, however
the NCP302HSN40T1G has a 10V voltage input limit which ruins the 30V needed and
offered by the LP2951.

How would you handle this problem?

And, regarding 1) can you suggest me a cheap and small logic level PMOS transistor?
It needs to pass (or not) +3.3V with minimal voltage drop even at 100mA peak current.
For "logic level" I mean that with the source at +3.3V and the gate at ground, it
should ~fully conduct.

Thanks a lot for any help.

Mario

2012\05\22@085553 by M.L.

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On Tue, May 22, 2012 at 2:43 AM, Electron <spam_OUTelectron2k4TakeThisOuTspaminfinito.it> wrote:
>
> Hi,
> I have a IC which, in the datasheet, is said to need a powerup rise time not
> slower than 100uS in order to initialize correctly. Effectively it doesn't work
> if the power ramps up slow, and there's no reset input, power must be disconnected
> in order to attempt a new successfull turn on.
>
> How would you ensure fast powerup rise time? The power turns on / ramps up very
> slowly, and I can't help it.
>

I'd use a circuit like this:
http://i.imgur.com/Hr8Aa.png

Replace R2 with the load.
D1 zener voltage is at least 700mV below the required turn-on voltage.
Add feedback resistor from load supply to base of Q1 to make it latch on.
-- Martin K

2012\05\22@092637 by Electron

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At 14.55 2012.05.22, you wrote:
{Quote hidden}

Yup, this is the PMOS solution.. I don't need the zener part as I have a
error signal I can use instead.

Just wanted to ask you, why R3 is just 2.2K? Wouldn't a higher value work
as well, and waste less power in the resistor?

Cheers,
Mario


>--
>Martin K.

2012\05\22@100711 by M.L.

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On Tue, May 22, 2012 at 9:26 AM, Electron <electron2k4spamKILLspaminfinito.it> wrote:
>>
>>I'd use a circuit like this:
>>http://i.imgur.com/Hr8Aa.png
>>
>>Replace R2 with the load.
>>D1 zener voltage is at least 700mV below the required turn-on voltage.
>>Add feedback resistor from load supply to base of Q1 to make it latch on.
>
> Yup, this is the PMOS solution.. I don't need the zener part as I have a
> error signal I can use instead.
>
> Just wanted to ask you, why R3 is just 2.2K? Wouldn't a higher value work
> as well, and waste less power in the resistor?
>
> Cheers,
> Mario
>

Yes, it might work fine but for two reasons:
1. I drew the schematic in 5 minutes.
2. Any current noise or signal introduced to the base of Q1 will be
multiplied by the beta of Q1. I would rather have R3 be smaller to
prevent accidental turn-on. After building the circuit I would
evaluate whether R3 could be larger.

-- Martin K

2012\05\22@141535 by Electron
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At 16.06 2012.05.22, you wrote:
{Quote hidden}

Yup, I understand the principle behind it, it's sane and safe. Expecially
on noisy environments (like my application) one has to keep the impedances
as low as possible, I have also low power constraints so a good compromise
is best found on the oscilloscope and various trials.

Thanks a lot, after evaluating various other solutions, like the NCP349 monitor,
I decided that the only one that will let me be in control of ramp up times
and more is a discrete solution. So it means PMOS driven by the error flag
of the linear regulator, through a NPN transistor. 7 extra components, more
hand soldering, but anyhow that's how it has to be done.

Cheers,
Mario


>
>--
>Martin K.
>

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